Whenever an integrated circuit (IC) is fabricated, it still needs to be connected to other elements; implemented with heat dissipation function; and protected by a housing, and thus a semiconductor packaging process follows. Semiconductor package structures can be relatively simple or complicated, and the number of pins in a semiconductor package is rapidly increasing due to the increasing integration from the development of ultra large-scale integration (ULSI). Conventional package structures generally provide IC chips with protection, power, heat dissipation and connections to other elements, but the purpose of modern package structures is changed to enabling the packaged IC chips to be compatible with next-level packaging.
For dealing with the trend of 3C products towards shortness, smallness, lightness and thinness, the flip-chip technology has become one of the most important packaging technologies. In the flip-chip technology, the technique for fabricating solder bumps is quite critical to the connection performance of semiconductor devices.
Referring to FIG. 1A to FIG. 1C, FIG. 1A to FIG. 1C are schematic diagrams showing the structure of a conventional solder bump and the fabrication process thereof. Such as shown in FIG. 1A, a bond pad 30 is formed between a wafer 10 and a passivation layer 20, and an under bump metallurgy (UBM) layer 22 is formed over the passivation layer 20 and the bond pad 30. Thereafter, such as shown in FIG. 1B, a high lead solder 50 is formed on the bond pad 30 under via the blocking of a photoresist layer 40 by electroplating or printing. Then, the photoresist 40 and a portion of the UBM layer 22 thereunder are removed, and a reflow step is performed subsequently for melting and forming the high lead solder 50 as a spherical solder bump 60 shown in FIG. 1C.
Referring to FIG. 1D to FIG. 1F, FIG. 1D to FIG. 1F are schematic diagrams showing a conventional flip-chip packaging process. Such as shown in FIG. 1D, the wafer 10 having the solder bumps 60 is turned upside down with flux applied on the solder bumps 60, and then the solder bumps 60 are mounted on a substrate 70. Such as shown in FIG. 1E, a reflow step is then performed under the reflow temperature of 320° C. to melt the solder bumps 60 for being attached to the substrate 70. Thereafter, such as shown in FIG. 1F, due to large stress difference between the wafer 10 and the substrate 70, cracks are easily to be caused at junction surfaces, i.e. the solder bumps 60, so that an underfill material 80 is filled among the solder bumps for distributing the stress on the entire underfill material 80, thereby reducing the stress exerted on each of the solder bumps 60, thus promoting reliability, wherein the underfill material 80 can be such as epoxy resin.
However, since the etching selectivity between the solder bumps 60 and the UBM layer 22 is poor, the step of etching the UBM layer 22 is difficult to be controlled. Further, the strength and capacitance density of the solder bumps 60 are not sufficient for fabricating high-speed charging and discharging elements. In addition, the conventional process needs to use the reflow steps, thus making the entire process quite complicated.
Hence, there is a need to develop a flip-chip packaging process using a copper pillar as a bump structure for overcoming the conventional process's disadvantages of insufficient strength and capacitance density of the solder bumps; having difficulty in controlling the step for etching the UBM layer; and requiring the relfow steps.